CHPC National Meeting Pre-Conference Workshops

All Pre-Conference workshops are taking place at Durban International Convention Centre, 45 Braam Fischer Road, Durban, South Africa

Exact venues will be advised by individual workshop facilitator.

All registrations to the Pre-Conference Workshops are complimentary. Registration fee is only applicable if delegates are attending the CHPC National Meeting 2012

T1: Application and Personality Development for Convey Hybrid-Core Computers (2 days)

Convey Hybrid-Core systems accelerate applications by applying hardware acceleration to processing or memory intensive algorithms. This hardware acceleration is delivered in the form of "personalities" that can be reloaded dynamically on the FPGA-based coprocessor in a Convey system. Convey has developed a suite of personalities that improve the performance of commonly used applications, in areas such as bioinformatics. Convey also provides a Personality Development Kit, which enables end users to develop custom personalities for Convey Systems.

This workshop will provide an overview of the Convey architecture and how personalities can exploit the architecture to accelerate applications. It will include an explanation of the Convey Bioinformatics Suite, including which applications are accelerated, and how those applications were implemented to maximize performance on the Convey system. It will also cover programming concepts, such as how to determine which applications will map well to the architecture and how to maximize performance. Finally, it will provide a detailed description of the Personality Development Kit used to development custom personalities, including hardware interfaces, simulation environment, tool flow and programming models.

T2: Python for High Performance Computing: MPI (1 day)

Python is a modern high level programming language that encompasses procedural, object-oriented and functional programming paradigms in a clean and concise syntax. Its ease of use, shallow learning curve and powerful constructs have made it the fastest growing language for scientific computing. Coupled with powerful, fast and efficient modules for numeric arrays, linear algebra and sparse matrix operations, along with modules for visualization, interfacing to high level file formats, Python now includes access to the message passing interface (MPI) library and the CUDA system for Nvidia GPUs.

This one day workshop is aimed at graduate students and practitioners in Science and Engineering who would like to use Python as an advanced numerical environment for high performance computing. The tutorial will take the form of lectures on python for HPC, including hands-on practical sessions. Topics to be covered:

using message passing for HPC clusters with mpi4py

accelerating vector-matrix operations on Nvidia GPUs with pycuda

reading/writing NetCDF and HDF5 files with python

visualization, pre- and post-processing with python

using ipython and parallel-ipython as numerical workbench

T3: Rapid Prototyping with GPUs: PyCUDA, Thrust and Octave

In this tutorial, participants will be introduced to techniques for general purpose programming on the GPU. Programming languages used to interface with the GPU will include Python, C++ and Octave. Three classes of HPC problems will be used as case studies, these include N-body problems, linear algebra and Monte Carlo simulation. The hands-on component of the tutorial will focus on the tools used for compiling, benchmarking, profiling and debugging a GPU application in either PyCUDA (Python), Thrust (C++) or Octave.

T4: Intel® Xeon® Phi (MIC) programming [1 day]

Schedule: Tue Dec 4, 2012. 8:30am - 5:00pm
Presenter: Rama Malladi

Programme Outline:

Introduction & Architecture Overview

Programing Model for Intel Xeon Phi

Using MKL & MPI on Intel Xeon and Xeon Phi

Performance Analysis and Optimizations

The objective of this workshop is to provide an insight into the Intel Xeon Phi architecture, the programming models and tools available with specific focus on techniques for obtaining best performance on Intel Xeon and Intel Xeon Phi architectures. We assume the audience would be software developers with programming knowledge in C++/Fortran and have basic familiarity with software programming and optimizations.

T5 NAG Optimisation & Scaling (2 days)

This course covers each of the major stages in writing efficient parallel scientific software, from generating correct code through understanding performance characteristics to optimising the time to solution.

The first day starts by looking at tools to help debug code, covering various methodologies for doing so, and includes exercises using the free software GDB and Valgrind. The day concludes with an introduction to modern processor architecture (focusing on x86 multicore architecture) and the aims of profiling. Profiling is continued on the second day with exercises making use of the free tools GNU gprof and Scalasca, covering how to interpret the data that these tools generate so as to discover possibilities for optimisation. Following on there is an introduction to serial optimisation techniques, from use of the compiler and libraries to more complex code reorganisations.

Throughout the course attendees will have extensive hands-on experience of the tools through exercises in addition to lectures.

Prerequisites: Experience in scientific programming in Fortran or C in a UNIX environment. For instance, one should be able to: connect to a machine remotely (e.g. using ssh), use basic UNIX commands, edit a source file, and understand the elementary steps in compiling object files and creating executables.

After Course Attendees Will: be able to use tools to debug and profile parallel or serial code effectively and identify and implement basic optimisations.

T7: Administration of High Performance Computing Systems (1 day) -
This is a workshop designed for Systems Administrators of Cluster ONLY.

The session covers the various aspects of technology and science applied in the CHPC - Sun cluster. It will present the importance and usage of different administrative components running in the cluster such as file system, scheduler, compilers and libraries used to simulate parallel programs in the supercomputing system. Some vital information about running and integrating applications in the parallel system will also be discussed.

The training will consist of talks followed by practical exercises. Attendees of this workshop might also wish to attend the Q&A Session of CHPC ICT Support (main conference session).

FORUMS

F1 CHPC Industrial Advisory Council (half-day)

This is a unique opportunity for South African companies to provide advice to CHPC on policy, strategy, and implementation as it pertains to industry. The CHPC Industrial Advisory Council will meet one to two times a year, will receive periodic updates on CHPC activities, and will be consulted during the course of the year. The council will be a forum to identify and discuss competitive issues around HPC adoption, use, and more generally industrial computing for design, manufacturing, and services that are important to the South African economy. Participation in this session is by invitation only.

F2 African HPC and Data Research Partnership (half-day)

In consultation with participants, the workshop aims to consolidate a borderless synergy amongst African stakeholders, formulate a sustainable partnership model and define a few selective pilot projects which can serve as a foundation towards the future development of this noteworthy partnership. Participation in this session is by invitation only.

F3 HPC Cyber Infrastructure Ecosystem

The forum is directed at developing a strategy to facilitate equitable access to both small scale and high-end computational resources to the research community. Participation in this session is by invitation only.



Home Presentations		CHPC National Meeting Pre-Conference Workshops All Pre-Conference workshops are taking place at Durban International Convention Centre, 45 Braam Fischer Road, Durban, South Africa Exact venues will be advised by individual workshop facilitator. All registrations to the Pre-Conference Workshops are complimentary. Registration fee is only applicable if delegates are attending the CHPC National Meeting 2012 T1: Application and Personality Development for Convey Hybrid-Core Computers (2 days) Convey Hybrid-Core systems accelerate applications by applying hardware acceleration to processing or memory intensive algorithms. This hardware acceleration is delivered in the form of "personalities" that can be reloaded dynamically on the FPGA-based coprocessor in a Convey system. Convey has developed a suite of personalities that improve the performance of commonly used applications, in areas such as bioinformatics. Convey also provides a Personality Development Kit, which enables end users to develop custom personalities for Convey Systems. This workshop will provide an overview of the Convey architecture and how personalities can exploit the architecture to accelerate applications. It will include an explanation of the Convey Bioinformatics Suite, including which applications are accelerated, and how those applications were implemented to maximize performance on the Convey system. It will also cover programming concepts, such as how to determine which applications will map well to the architecture and how to maximize performance. Finally, it will provide a detailed description of the Personality Development Kit used to development custom personalities, including hardware interfaces, simulation environment, tool flow and programming models. T2: Python for High Performance Computing: MPI (1 day) Python is a modern high level programming language that encompasses procedural, object-oriented and functional programming paradigms in a clean and concise syntax. Its ease of use, shallow learning curve and powerful constructs have made it the fastest growing language for scientific computing. Coupled with powerful, fast and efficient modules for numeric arrays, linear algebra and sparse matrix operations, along with modules for visualization, interfacing to high level file formats, Python now includes access to the message passing interface (MPI) library and the CUDA system for Nvidia GPUs. This one day workshop is aimed at graduate students and practitioners in Science and Engineering who would like to use Python as an advanced numerical environment for high performance computing. The tutorial will take the form of lectures on python for HPC, including hands-on practical sessions. Topics to be covered: using message passing for HPC clusters with mpi4py accelerating vector-matrix operations on Nvidia GPUs with pycuda reading/writing NetCDF and HDF5 files with python visualization, pre- and post-processing with python using ipython and parallel-ipython as numerical workbench T3: Rapid Prototyping with GPUs: PyCUDA, Thrust and Octave In this tutorial, participants will be introduced to techniques for general purpose programming on the GPU. Programming languages used to interface with the GPU will include Python, C++ and Octave. Three classes of HPC problems will be used as case studies, these include N-body problems, linear algebra and Monte Carlo simulation. The hands-on component of the tutorial will focus on the tools used for compiling, benchmarking, profiling and debugging a GPU application in either PyCUDA (Python), Thrust (C++) or Octave. T4: Intel® Xeon® Phi (MIC) programming [1 day] Schedule: Tue Dec 4, 2012. 8:30am - 5:00pm Presenter: Rama Malladi Programme Outline: Introduction & Architecture Overview Programing Model for Intel Xeon Phi Using MKL & MPI on Intel Xeon and Xeon Phi Performance Analysis and Optimizations The objective of this workshop is to provide an insight into the Intel Xeon Phi architecture, the programming models and tools available with specific focus on techniques for obtaining best performance on Intel Xeon and Intel Xeon Phi architectures. We assume the audience would be software developers with programming knowledge in C++/Fortran and have basic familiarity with software programming and optimizations. T5 NAG Optimisation & Scaling (2 days) This course covers each of the major stages in writing efficient parallel scientific software, from generating correct code through understanding performance characteristics to optimising the time to solution. The first day starts by looking at tools to help debug code, covering various methodologies for doing so, and includes exercises using the free software GDB and Valgrind. The day concludes with an introduction to modern processor architecture (focusing on x86 multicore architecture) and the aims of profiling. Profiling is continued on the second day with exercises making use of the free tools GNU gprof and Scalasca, covering how to interpret the data that these tools generate so as to discover possibilities for optimisation. Following on there is an introduction to serial optimisation techniques, from use of the compiler and libraries to more complex code reorganisations. Throughout the course attendees will have extensive hands-on experience of the tools through exercises in addition to lectures. Prerequisites: Experience in scientific programming in Fortran or C in a UNIX environment. For instance, one should be able to: connect to a machine remotely (e.g. using ssh), use basic UNIX commands, edit a source file, and understand the elementary steps in compiling object files and creating executables. After Course Attendees Will: be able to use tools to debug and profile parallel or serial code effectively and identify and implement basic optimisations. T7: Administration of High Performance Computing Systems (1 day) - This is a workshop designed for Systems Administrators of Cluster ONLY. The session covers the various aspects of technology and science applied in the CHPC - Sun cluster. It will present the importance and usage of different administrative components running in the cluster such as file system, scheduler, compilers and libraries used to simulate parallel programs in the supercomputing system. Some vital information about running and integrating applications in the parallel system will also be discussed. The training will consist of talks followed by practical exercises. Attendees of this workshop might also wish to attend the Q&A Session of CHPC ICT Support (main conference session). FORUMS F1 CHPC Industrial Advisory Council (half-day) This is a unique opportunity for South African companies to provide advice to CHPC on policy, strategy, and implementation as it pertains to industry. The CHPC Industrial Advisory Council will meet one to two times a year, will receive periodic updates on CHPC activities, and will be consulted during the course of the year. The council will be a forum to identify and discuss competitive issues around HPC adoption, use, and more generally industrial computing for design, manufacturing, and services that are important to the South African economy. Participation in this session is by invitation only. F2 African HPC and Data Research Partnership (half-day) In consultation with participants, the workshop aims to consolidate a borderless synergy amongst African stakeholders, formulate a sustainable partnership model and define a few selective pilot projects which can serve as a foundation towards the future development of this noteworthy partnership. Participation in this session is by invitation only. F3 HPC Cyber Infrastructure Ecosystem The forum is directed at developing a strategy to facilitate equitable access to both small scale and high-end computational resources to the research community. Participation in this session is by invitation only. Terms of Use \| Sitemap \| Copyright © - 2013 Walthers & OJB Web Development.